\ OVERVIEW
MEMS manufacturing
Our cleanroom runs MEMS production on 4- and 6-inch wafers in silicon, glass, flexible substrates and custom COC/COP polymer. We take them through dicing, packaging, PCB and plastic integration rather than stopping at bare die. Multi-layer SU-8 lithography holds 2 µm features at aspect ratios up to 20:1; we deep-etch silicon and glass and, for our own tooling, bulk titanium and tungsten. The team has over thirty years of MEMS industry experience.
2 µm
lithography feature size, multi-layer SU-8
20:1
aspect ratio
100 nm
UV nanoimprint & two-photon resolution
4 & 6 inch
wafer sizes, in-house cleanroom
30+ years
team experience in the MEMS industry
\ CAPABILITIES
Capabilities and technical specifications
Mask to integrated device in house — lithography, deposition, etching, wafer bonding, dicing, then wire bonding, flip-chip and plastic integration — on silicon, glass, flexible substrates and custom COC/COP wafers. The same line makes the 2 µm molds behind our injection molding and PDMS pages.
Fabrication capability
We confirm substrate-specific etch depths, via dimensions and overlay accuracy for your stack in the DFM review.
Lithography feature size
2 µm; resolution to 100 nm via UV nanoimprint and two-photon routes
Aspect ratio
Up to 20:1
Layer count
Multi-layer lithography; single- and multi-layer molds
Etching
High-aspect-ratio etching in silicon and glass; deep bulk-metal etching for internal tooling
Vias
2D interposers and through-silicon via (TSV)
Dicing
Wafer dicing with edge control for microfluidic interfaces
Integration
Die-to-PCB wire bonding and flip-chip; bonding into polymer devices; flexible-substrate assembly
Testing
Custom test protocols; automated test equipment (ATE) available
Process modules
SU-8 lithography
Multi-layer lithography · 2 µm feature size · aspect ratios up to 20
Deep etching
High-aspect-ratio etching of silicon and glass; deep bulk-metal etching of titanium and tungsten for our own tooling
Via technology
2D interposers · through-silicon via (TSV)
Custom polymer wafers
COC and COP wafers made to your specification, with MEMS processes run directly on them
PCB integration
MEMS die onto PCB — wire bonding, flip-chip and electrical breakout into the finished assembly
Plastic integration
Packaging, bonding and hybrid workflows — MEMS parts into polymer devices
Flexible substrates
MEMS on flexible substrates for conformal and implantable-class devices
Microfluidic interfaces
Complex channel design · dicing with edge control
MEMS testing
Custom test protocols · ATE available
MEMS is also the tooling engine behind our other processes.
The 2 µm minimum feature quoted on our injection molding page is achievable because the mold is made here, by MEMS. Precision metal molds for thermoplastic molding and SU-8 molds for PDMS production are both fabricated by MEMS photolithography. A molder buying tooling externally is limited by what a machine shop can cut; we are limited by what lithography can define.
\ MATERIALS
Substrates for MEMS fabrication
Silicon is the standard; glass, flexible carriers and custom polymer wafers are chosen for optics, conformality or the chemistry of the device.
Silicon
WHAT WE DO WITH IT
Full MEMS flow — lithography, DRIE, deposition, vias, bonding
WHY IT MATTERS
The standard MEMS substrate
Glass
WHAT WE DO WITH IT
Etching, through-glass vias, anodic bonding, optical-grade surfaces
WHY IT MATTERS
Near-zero autofluorescence — fused silica, the reference substrate for it, runs 30–60× below standard soda-lime — and optical transparency; the glass-only route is on the glass microfluidics page
Custom COC / COP wafers
WHAT WE DO WITH IT
Polymer wafers made to your specification, with MEMS processes run directly on them
WHY IT MATTERS
Microfluidic-grade optical polymers with wafer-level patterning — rarely available anywhere
Flexible substrates
WHAT WE DO WITH IT
MEMS on flexible carriers for conformal devices
WHY IT MATTERS
Wearables and neural interfaces, where rigid silicon cannot go
Tooling materials — bulk titanium and tungsten
We deep-etch solid titanium and tungsten wafers to produce our own micro-tooling. These are not sold as substrates or devices, but the process is part of why our molds reach 2 µm, and the tungsten process is published.
ETCH DEPTH
> 300 µm in patterned bulk tungsten
ETCH RATE
2.73 µm/min
ETCH SELECTIVITY
35
ASPECT RATIO
> 20
FEATURE SIZE
< 3 µm
SURFACE ROUGHNESS
Ra 30 nm
Grade-level substrate data and hybrid constructions are in the Materials guide.
\ PROCESS
Fabrication process
One wafer flow from mask to measured device; the etch and bonding steps change with the substrate.
Design and mask
We choose substrate, stack and bonding route together, check the layout against feature size, aspect ratio and dicing lanes, then make the masks.
Free DFM review
Wafer bonding
Surface activation, then anodic, fusion or laser bonding — glass-to-silicon and glass-to-glass at wafer level, under alignment.
Anodic · fusion · laser
Lithography
Photolithography, UV nanoimprint or two-photon; multi-layer SU-8 where the mold or the device needs height.
2 µm · resolution to 100 nm
Dicing and packaging
Wafer dicing with edge control, then wire bonding, flip-chip, PCB and plastic integration into the finished assembly.
4- and 6-inch wafers
Thin-film deposition
Sputtering, PECVD and LPCVD for metallization, dielectrics and passivation — electrodes and heaters where the device is active.
Sputtering · PECVD · LPCVD
Metrology and test
SEM, confocal and profilometry across the wafer; electrical test to custom protocols, with ATE where the volume justifies it.
Custom protocols · ATE
Etching
Deep silicon (DRIE), NLD and glass etch; the same chambers deep-etch bulk tungsten and titanium for our tooling.
Aspect ratio to 20:1
\ QUALITY CONTROL
Quality control
Dimensional and surface
SEM, white-light interferometry, confocal and stylus profilometry, selected by feature scale
Electrical
Custom test protocols; ATE available
Environment
In-house cleanroom wafer processing
Wafer inspection
In-process inspection across the wafer, not sampled at the end
Delivery protection
Protective film applied to the surface; wafer-box packaging
Quality system
ISO 13485 certified · FDA registered
\ LEAD TIME & MOQ
Lead time & MOQ
Standard lead time
4–6 weeks. We evaluate complex process flows case by case and flag them in the quote.
Beyond the wafer
Dicing, packaging, PCB integration, bonding into polymer devices and assembly, all in house
Minimum order
At least one 4-inch wafer
Indicative pricing
NRE from $2,500 — design, mask work, process development and first-article validation; a variant of a device we already build sits at the floor, a novel flow above it
Delivery format
Protective film applied to the surface, wafer-box packaging
\ SHOWCASE
Case studies and applications
Applications
\ TESTIMONIALS
“
High-quality micro-patterned electrodes are a crucial part of SynVivo’s product portfolio. HiComp delivered them on schedule at a competitive price.
Jenna M Rosano
Senior Research Scientist, SynVivo, Huntsville, Alabama
FAQ
